1. Field of the Invention
The present invention generally relates to clock adjustment apparatus for data reproduction systems and apparatus having data reproduction systems including such clock adjustment apparatus, and more particularly, to a clock adjustment apparatus for a data reproduction system of a data recording apparatus such as an optical disk apparatus, a magneto-optical disk apparatus or a magnetic disk apparatus, and an apparatus having a data reproduction system including such a clock adjustment apparatus. A magneto-optical disk apparatus, for example, requires an increasingly high recording density of a recording medium, and therefore, needs a data recording/reproduction method with higher accuracy. Adopted as one of such methods is a combination of recording data modulated to a partial response (PR) waveform onto a magneto-optical disk and sampling a readout signal from the magneto-optical disk at a predetermined sampling frequency so as to detect maximum likelihood data through, what is called, the Viterbi decoding detection (or the maximum likelihood sequence estimation: MLSE). Hereinafter, this combination method is referred to as a PRML method.
With respect to the PRML method, it is important to provide phase compensation so that a quantized readout signal can be sampled in synchronism with a clock signal.
2. Description of the Related Art
Regarding a data reproduction system for reproducing recorded data in accordance with the Viterbi algorithm from sampled values obtained by sampling readout data from a recording medium in synchronism with a clock signal, it is necessary to adjust the phase of the clock signal so that the best sampled values can be obtained.
A conventional clock adjustment apparatus for the data reproduction system estimates the phase error of the clock signal by using a value (for example, a center value of the readout signal) calculated in the process of reproducing recorded data through the Viterbi algorithm so as to control the phase of the clock signal by using the phase error.
According to such a conventional clock adjustment apparatus, the overall structure of the data reproduction system including the clock adjustment apparatus can be simplified.
On the other hand, the above-described data reproduction system requires a higher-speed clock signal because of a higher recording density of the recording medium.
However, the conventional clock adjustment apparatus, which estimates the phase error of the clock signal by using the processed readout data through the Viterbi algorithm, has difficulty in obtaining such a higher-speed clock signal necessary to guarantee the sampling of the readout signal at the right phase.